The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a method of forming dual channel complementary metal oxide semiconductor (CMOS) fin field effect transistors (i.e., finFETs). The present application also relates to a semiconductor structure that can be formed by the method.
For more than three decades, the continued miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continued scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, further methods for improving performance in addition to scaling have become critical.
The use of non-planar semiconductor devices such as, for example, semiconductor fin field effect transistors (FinFETs) is the next step in the evolution of complementary metal oxide semiconductor (CMOS) devices. Semiconductor fin field effect transistors (FETs) can achieve higher drive currents with increasingly smaller dimensions as compared to conventional planar FETs. In order to extend these devices for multiple technology nodes, there is a need to boost the performance with high-mobility channels.
Dual channel CMOS having different semiconductor channel materials is needed for 10 nm and beyond technologies. For example, silicon (Si) fins are needed for nFinFET devices, while silicon germanium alloy (SiGe) fins are needed for pFinFET devices. Due to the material property difference, processing semiconductor fins having different channel mobility still has some unique challenges. For example, Si and SiGe have different etch rates which can result in Si fins and SiGe fins that have completely different critical dimensions including, for example, different fin widths. Different fin widths can cause unwanted process, device, and design complexities.
In view of above, there is a need to provide a method for forming dual channel CMOS FinFETs in which the Si fins and the SiGe fins have the same width and the same critical dimension.